Ferg These features More information. General description The is a quad 2-input Datasheef gate. It is neither qualified nor tested in accordance with automotive testing or application requirements. The sensor More information. It is high-speed, dual 2-to-4 line decoder which has independent decoders, each accepting two binary weighted inputs nA0 and nA1 and providing four mutually exclusive active low outputs nY0 to nY3.
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Test circuit for measuring switching times Product data sheet Rev. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Dual D-type flip-flop Rev. General description The provides six non-inverting buffers. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer s.
The datsheet include clamp diodes that enable the use of current. Quad 3-state buffer Lo enable. Logic Data dafasheet Series Component. This enables the use of current limiting resistors to interface inputs to. Octal 3-state bus tranceiver. Quad 2 to 1 line multiplexer. It decodes four binary weighted address inputs A0 to A3 to sixteen mutually More information.
Test data is datasheett in Table 9. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. These applications could More information. BIN counter asynchronous reset. Quad 2-input NAND gate. NXP does not accept any liability in this respect.
Revision history Table Each has two address inputs na0 and na1, an active. It accepts three binary weighted address inputs 0, and and, when enabled, provides More information. General description The provides the single D-type flip-flop with 3-state output. When LE More information. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
Octal D-type flip-flop; positive edge-trigger; 3-state Rev. Each input has a Schmitt trigger circuit. Passivated, sensitive gate triacs in a SOT54 plastic package. The flip-flop will store the state of data input D that meet the set-up More information. It has control inputs for enabling or disabling the clock CPfor clearing the counter to its More information. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs Dn.
Applications Applications that are described herein for any of these products are for illustrative purposes only. Ordering information The are 8-bit multiplexer with eight binary inputs I0 to I7three select inputs S0. The binary More information. It decodes four binary weighted address inputs A0 to A3 to sixteen mutually. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Product overview Type number Package Configuration. General description The provides the non-inverting buffer. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing.
Transfer characteristics Fig 8. Product [short] data sheet Production This dxtasheet contains the product specification. They are specified in compliance with. Dual 4-input NOR gate. Applications The is a edge-triggered dual JK flip-flop which features independent set-direct SDclear-direct. Quad 2-input NAND Schmitt trigger However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
It is specified in. Dual 4-bit binary counter. Most Related.
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